Most GPU buyers focus on SM count, memory bandwidth, and CUDA cores. Few realize that every Nvidia GPU actually hides 10 to 40 RISC-V microcontroller cores. They do not render graphics or do AI math; instead they handle video encode/decode, power management, security engines, kernel driver offload, and other "invisible work."

Falcon Retires, RISC-V Rises

Nvidia first introduced its proprietary Falcon (FAst Logic CONtroller) microcontroller on the 2005 G98 GPU. Falcon is a 32-bit core without a data cache, and can no longer keep up with the complexity AI workloads demand. After evaluating Arm and MIPS, Nvidia settled on RISC-V as Falcon's successor in 2015.

By 2024, Nvidia estimated its GPUs that year alone contained around 1 billion RISC-V cores. From Turing (2018) to Ampere (2020), Ada/Hopper (2022), and Blackwell (2024), every generation deepens the RISC-V dependency.

Three Cores, One Subsystem

Nvidia has at least three RISC-V microcontroller cores: NV-RISCV32 (RV32I-MU, in-order single-issue, 1.8 GHz, 1.8 CM/MHz), NV-RISCV64 (RV64I-MSU, out-of-order dual-issue, 2 GHz, 5 CM/MHz, supports SMP), and NV-RVV (NV-RISCV32 plus a 1024-bit vector extension).

Around these three, Nvidia built a unified subsystem called Peregrine: it parameterizes the RISC-V core, caches, TCM, interrupt controller, DMA, RSA/PKA, and AES engine into a configurable "kit" for the GPU control plane. Nvidia also added 20+ custom extensions covering 64-bit physical addresses, 2KB pages, ICD secure debug, ROM memory protection, and cache operations.

GSP and DLA: Two Pieces Doing Real AI Work

The two applications most relevant to AI inference are concrete.

The GPU System Processor (GSP) sits between the host CPU and the GPU, communicating over PCIe and directly controlling the GPU's hardware units and video memory. GSP uses multiple RV64 cores plus a coherent fabric and unified TCM/cache. It does three things: offloads kernel drivers, reduces the GPU's exposure surface to the CPU, and encapsulates GPU low-level details. It supports a multi-partition mode — one GPU is sliced into multiple vGPUs distributed across different tenants' Guest VMs. This architecture directly serves the multi-tenant scenario of cloud LLM inference and underpins confidential computing.

The Deep Learning Accelerator (DLA) is Nvidia's fixed-function inference IP, also running on RISC-V — NV-RISCV32 for scalar work, NV-RVV for vector. The compiler can fuse multiple operators into a single RVV kernel. In Orin and other edge AI chips, DLA runs TensorRT model offload paths away from the CPU/GPU, tightly tied to large-model deployment.

Final Take

What Nvidia disclosed at RISC-V Summit 2024 reveals something the AI compute narrative tends to obscure: the modern GPU is already a SoC. Beyond CUDA cores, it carries a control plane and acceleration subsystem built on an open ISA. The next time someone claims RISC-V is still a "data center experiment," hit them with NV-RISCV32/64/RVV, GSP, DLA, and Peregrine.