On June 27, Qualcomm unveiled a comprehensive data-center roadmap, with the HBC (High-Bandwidth Computing) architecture at its core. Unlike the previous "phone-side" HBC story, this is the data-center variant — 3D-stacked memory and compute units, designed for LLM decoding.
The technical path: HBC uses through-silicon-via (TSV) 3D stacking to place DRAM directly on top of the compute die, reducing memory-bandwidth distance from centimeters (traditional PCB) to microns (3D stack). Compared with HBM, HBC further halves the memory access latency and boosts bandwidth by another 2-3×.
The LLM decode scenario is the showcase: traditional HBM-based decoders are bandwidth-bound — each token generation requires loading the full model weights, and the tokens-per-watt metric is stuck in the 0.1-0.2 tok/J range. HBC pushes the memory closer, and the test chip has demonstrated 0.6-0.8 tok/J on a 70B-class model — a 3-6× improvement.
The roadmap: first-generation HBC data-center products in 2026, second-generation with 5nm compute die in 2027, and a phone-side variant landing in 2028 (per the previously announced plan). Qualcomm has also opened the HBC SDK, allowing LLM inference frameworks to optimize specifically for the HBC memory topology.
The bigger signal: the LLM inference bottleneck is moving from "compute" to "memory bandwidth," and 3D stacking is the most direct answer. HBC is Qualcomm's bet against NVIDIA's HBM4+Blackwell dominance — and on the phone side, it's a clear pre-emptive strike against Apple's M-series and Intel's Lunar Lake.