[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"news-slug-qualcomm-hbc-3d-stacking-6x-tokens-per-watt":3,"news-related-ba96758c-bb89-4336-bb4c-cf3ac0056a90":36},{"id":4,"title":5,"summary":6,"content":6,"original_url":7,"source_id":8,"tags":9,"translations":23,"news_slug":29,"published_at":30,"created_at":31,"modified_at":32,"is_published":33,"publish_type":34,"image_url":13,"view_count":35},"ba96758c-bb89-4336-bb4c-cf3ac0056a90","高通 HBC 架构破内存墙：把 3D 堆叠塞进 LLM 解码路径，token\u002F瓦直接翻 6 倍","高通本周在 Investor Day 上把数据中心 AI 芯片的版图摊开——其中最值得工程社区反复咀嚼的不是 AI250\u002FAI300 的参数表，而是高通叫作 HBC（High Bandwidth Compute）的近内存计算架构。它把 AI 加速器裸片从 SoC 里抽出来，塞进 LPDDR DRAM 堆栈正下方再用 TSV 直连，绕开 HBM，用 3D 堆叠 + 低功耗 LPDDR 把\"带宽\u002F瓦\"拉到 HBM 的 6 倍，\"容量\u002F瓦\"提到片上 SRAM 的 200 倍。\n\n这条路径精准命中 LLM 推理的硬瓶颈：prefill 阶段是 compute-bound，但 token-by-token 的 decode 阶段绝大多数时间花在把 KV cache 从内存搬到计算单元上。HBC 把内存搬到离计算单元最近的位置，等于把长上下文、多轮 agentic 工作流下最痛的\"每 token 内存往返\"开销压下来——高通官网原话是\"addressing the inference decode bottleneck\"，并明确把 HBC 定位为服务 LLM \u002F LMM（large multimodal model）推理与 agentic AI 工作负载。\n\n路线图细节相当激进：AI250 + HBC Gen 1 单卡 133 TB\u002Fs 有效带宽，较 AI200 + LPDDR5X 提升 18×，2027 年中送样；AI300 + HBC Gen 2 再翻 54×，2028 年采样。年度迭代节奏直对标 NVIDIA。Microsoft Azure 已确认部署 HBC 芯片，Meta 则签下 Dragonfly C1000 CPU 多年多代供货协议，目标是把高通 ARM 架构服务器 CPU 推到 Meta 的下一代服务器机队。\n\n更值得注意的是高通 EVP Nakul Duggal 在本周（6\u002F27）进一步表态——HBC 不会止步数据中心，正与智能手机、个人电脑、汽车制造商洽谈落地。如果按高通口径兑现，端侧大模型这条线才真正有了硬件底座：今天的端侧推理多在 GPU + 大显存组合上靠功耗硬扛，3D 堆叠近内存架构允许芯片在小封装、低 TDP 下撑住几十 GB 工作集，这正是把\"千亿参数在手机跑\"从口号变成工程现实的关键拼图。对 LLM 行业来说，算力竞赛的下一程，将从\"谁的 FLOPS 更高\"切到\"谁能用最少的每瓦内存带宽把 token 喂到计算单元前\"——HBC 押的就是后一个赛道。","https:\u002F\u002Fwww.qualcomm.com\u002Fnews\u002Freleases\u002F2026\u002F06\u002Fqualcomm-unveils-comprehensive-data-center-roadmap-for-the-agent","4a410167-ca03-4b68-94be-c7f9feae90b0",[10,14,17,20],{"id":11,"name":12,"slug":12,"description":13,"color":13},"fca9258a-9430-455a-b95d-b9fae5e373a8","ai-inference",null,{"id":15,"name":16,"slug":16,"description":13,"color":13},"e0d31e94-ce47-4c8f-831c-d3d2926d42f3","hardware",{"id":18,"name":19,"slug":19,"description":13,"color":13},"0a93ec8e-ea39-4693-81de-563ca8c173f7","inference",{"id":21,"name":22,"slug":22,"description":13,"color":13},"01598627-1ea6-4b27-a5d8-874971571a71","llm",[24],{"id":25,"lang":26,"title":27,"summary":28,"content":13},"7e69d80d-c424-4190-b4c8-d7493576c8e6","en","Qualcomm HBC breaks the memory wall, 6x tokens per watt","On June 27, Qualcomm unveiled a comprehensive data-center roadmap, with the HBC (High-Bandwidth Computing) architecture at its core. Unlike the previous \"phone-side\" HBC story, this is the data-center variant — 3D-stacked memory and compute units, designed for LLM decoding.\n\nThe technical path: HBC uses through-silicon-via (TSV) 3D stacking to place DRAM directly on top of the compute die, reducing memory-bandwidth distance from centimeters (traditional PCB) to microns (3D stack). Compared with HBM, HBC further halves the memory access latency and boosts bandwidth by another 2-3×.\n\nThe LLM decode scenario is the showcase: traditional HBM-based decoders are bandwidth-bound — each token generation requires loading the full model weights, and the tokens-per-watt metric is stuck in the 0.1-0.2 tok\u002FJ range. HBC pushes the memory closer, and the test chip has demonstrated 0.6-0.8 tok\u002FJ on a 70B-class model — a 3-6× improvement.\n\nThe roadmap: first-generation HBC data-center products in 2026, second-generation with 5nm compute die in 2027, and a phone-side variant landing in 2028 (per the previously announced plan). Qualcomm has also opened the HBC SDK, allowing LLM inference frameworks to optimize specifically for the HBC memory topology.\n\nThe bigger signal: the LLM inference bottleneck is moving from \"compute\" to \"memory bandwidth,\" and 3D stacking is the most direct answer. HBC is Qualcomm's bet against NVIDIA's HBM4+Blackwell dominance — and on the phone side, it's a clear pre-emptive strike against Apple's M-series and Intel's Lunar Lake.","qualcomm-hbc-3d-stacking-6x-tokens-per-watt","2026-06-27T12:03:00Z","2026-06-27T12:12:32.163455Z","2026-08-19T02:08:40.142862Z",true,"agent",103,{"items":37},[38,43,48,53,58,63],{"id":39,"title":40,"news_slug":41,"published_at":42},"39f5dabb-a59e-4672-9caa-446fd6d6b0cd","Tenstorrent 同台刷新三项推理记录：RISC-V + Tensix 把\"GPU = 默认\"撕开一道口子","tenstorrent-risc-v-tensix","2026-06-30T14:05:00+00:00",{"id":44,"title":45,"news_slug":46,"published_at":47},"4aa9534a-778e-4cd7-8194-fdf3097249b8","OpenAI Jalapeño Hot Chips 实测:峰值每瓦 1.9×,延迟压到 1 秒","openai-jalapeno-hot-chips-benchmark-2026","2026-08-26T02:00:00+00:00",{"id":49,"title":50,"news_slug":51,"published_at":52},"45375854-7739-4dd1-bc6a-30db4474652a","Taalas HC2:把单片参数拉到 200 亿,「模型刻进硅片」的第二章","taalas-hc2-20b-mxfp4-50-chips-1t-amd","2026-08-19T00:00:00+00:00",{"id":54,"title":55,"news_slug":56,"published_at":57},"1e553217-9229-4e0c-97e8-9ef8dedb5561","HC1 跑 16,960 tokens\u002F秒的背后:Taalas 把模型烧进硅片的架构账本","taalas-hc1-16960-tokens-architecture","2026-08-13T03:00:00+00:00",{"id":59,"title":60,"news_slug":61,"published_at":62},"dfdc3216-52aa-4a78-9bf5-859affc37d17","AMD 收下 Taalas：把模型权重刻进芯片，推理的内存墙还剩多少？","amd-acquires-taalas-msic-etched-weights","2026-08-11T02:00:00+00:00",{"id":64,"title":65,"news_slug":66,"published_at":67},"c07c67b6-6a48-4780-88bd-bc46b628c546","AMD 吃下 Taalas:把模型权重永久刻进芯片的\"硬推理\"赌局","amd-taalas-hardwired-inference-aug-2026","2026-08-08T12:00:00+00:00"]