[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"news-slug-taalas-hc2-20b-mxfp4-50-chips-1t-amd":3,"news-related-45375854-7739-4dd1-bc6a-30db4474652a":41},{"id":4,"title":5,"summary":6,"content":7,"original_url":8,"source_id":9,"tags":10,"translations":27,"news_slug":34,"published_at":35,"created_at":36,"modified_at":37,"is_published":38,"publish_type":39,"image_url":14,"view_count":40},"45375854-7739-4dd1-bc6a-30db4474652a","Taalas HC2:把单片参数拉到 200 亿,「模型刻进硅片」的第二章","AMD 收购 Taalas 后,第二代芯片 HC2 目标每片 200 亿参数,采用 MXFP4 数值格式,50 片 pipeline parallelism 即可拼出 1 万亿参数模型。","AMD 8 月 6 日收盘后宣布收购多伦多初创公司 Taalas,把「把大模型权重直接刻进芯片」这条路正式收进了 Instinct 体系。事件的第一章已经写完 —— 第一代测试芯片 HC1 用台积电 6nm 工艺跑 Llama 3.1 8B,做到 16,960 tokens\u002F秒,官方自称比英伟达 GPU 快 48 倍、比 Cerebras 加速器快 8.5 倍。但 Taalas 真正想交付的,其实是第二章:第二代芯片 HC2,目标每片 200 亿参数,采用 MXFP4 数值格式,2026 年夏至 2027 年初推出。\n\n## 从 8B 到 200 亿,差在哪儿\n\nHC1 的本质是「记忆 fabric + 计算 fabric」的双区结构:模型权重永久刻在 mask-ROM 的金属层里,KV 缓存和轻量适配器放在可写的 SRAM 里。它把「权重搬移到计算单元」这一最贵的瓶颈直接消掉,但代价是芯片锁死在某个具体的模型快照上 —— 一旦刻好,改不了。\n\nHC2 把这条路的代价压了下来。Taalas 在 The Next Platform 的一次访谈中估算,把权重刻进硅片的成本大约只有从头训练一个前沿模型的 1\u002F100。这意味着同一颗芯片里能容纳的权重规模,可以比上一代激进得多:从 8B 直接抬到 200 亿。TechTimes 的报道进一步指 HC2 将采用 MXFP4 这种行业标准的 4-bit 浮点格式,密度再上一个台阶,且对极端值和低比特量化的容忍度比 INT4 更好。\n\n## 50 片拼 1T:用 GPU 时代的老办法解决新问题\n\n只谈单片参数意义有限,真正有意思的是 Taalas 给出的扩展账本:50 片 HC2 用 pipeline parallelism 把权重切分,理论上就能跑 1 万亿参数的模型 —— 这正是当前最大规模开源与闭源模型所在的参数区间。换言之,HC2 不追求单片跑得最大,而是用「小颗粒、多芯片」的工程办法,把 MSIC(model-specific integrated circuit)这张牌推到能与 GPU 集群正面竞争的规模窗口。\n\n## AMD 的「tick-tock」算盘\n\nTaalas 进 AMD 体系后,大概率不是要取代 Instinct,而是要塞进 Helios 机柜做分层。一种已经在内部流传的部署模型是:Prompt 处理留在 GPU 上做(预填充是计算密集、对更新灵活度敏感),token 生成交给 Taalas 加速器(解码是访存密集、对单次延迟敏感,且模型一旦稳定就很少改动)。这种拆分与英伟达 2025 年底花约 200 亿美元拿下 Groq 授权许可的逻辑同源:GPU 厂商不再只卖 GPU,而是把专用推理硅挂在自己体系边上,一起卖给「agentic、always-on」的工作负载。\n\nAMD SVP of AI Vamsi Boppana 在公告中的措辞也印证了这一点:AMD 要构建一个「全栈 AI 平台」,让客户能为每一种 AI 工作负载挑选最合适的算力解 —— 这意味着 Instinct 与 Taalas 两条产品线会并行存在,而非互相替代。\n\n## 三个不能回避的代价\n\nHC2 解决的是「能不能做大」,没解决的是「能不能动」:\n\n- 模型锁死:一张芯片只能跑刻进去那一刻的模型。同一型号增量更新只需换两层金属层,成本可控;但要是换一个全新基座模型,就是完整流片。\n- 安全补丁失效:任何 jailbreak 或 prompt injection 一旦发现,刻在硬件里的版本没法热修。这把传统的「软件快速打补丁」变成「重新流片」,对长生命周期产品反而是优点,对持续迭代的产品反而是负担。\n- 面积代价:HN 讨论里有人估算过,4GB 权重用 mask-ROM 刻大约要 800mm²,而同样容量的 DRAM 只要 80mm² 左右,差一个数量级。这意味着短期内它进不了手机、笔记本,更适合长生命周期、固定模型的边缘 \u002F 嵌入式场景 —— 比如机器人、drive-thru 语音助手、视觉系统。\n\n## 所以呢\n\nHC2 不是 GPU killer,但它把「专用推理硅片」这条原本只在博客文章里出现的思路,拉到了可以正面承接 1 万亿参数模型的工程量级。AMD 现在手里同时有 Instinct GPU + Taalas MSIC 两张牌,关键问题是产品矩阵怎么排:什么时候让模型「毕业」到 Taalas 硅片上,什么时候继续留在可更新的 GPU 上 —— 这个判断会成为接下来两年所有想做大规模 agent \u002F 长上下文推理的团队,绕不开的工程参考点。\n\n原始出处:Taalas 把模型权重刻进芯片,而 HC2 把这件事推到了 200 亿参数 \u002F MXFP4 \u002F 50 片拼 1T 的下一章。技术细节详见 The Next Platform 访谈与 TechTimes 报道。","https:\u002F\u002Fwww.nextplatform.com\u002Fcompute\u002F2026\u002F02\u002F19\u002Ftaalas-etches-ai-models-onto-transistors-to-rocket-boost-inference\u002F4092140","edd2e36a-855e-4e24-a09b-3037b9154dc8",[11,15,18,21,24],{"id":12,"name":13,"slug":13,"description":14,"color":14},"fca9258a-9430-455a-b95d-b9fae5e373a8","ai-inference",null,{"id":16,"name":17,"slug":17,"description":14,"color":14},"40269b40-7942-4650-9672-ed2e6524d37a","ai-technology",{"id":19,"name":20,"slug":20,"description":14,"color":14},"e0d31e94-ce47-4c8f-831c-d3d2926d42f3","hardware",{"id":22,"name":23,"slug":23,"description":14,"color":14},"0a93ec8e-ea39-4693-81de-563ca8c173f7","inference",{"id":25,"name":26,"slug":26,"description":14,"color":14},"7e89b5cc-57db-4f37-bc6d-28919a73931c","model-release",[28],{"id":29,"lang":30,"title":31,"summary":32,"content":33},"61f7aa3c-8a55-4190-a53a-8eded52092ad","en","Taalas HC2: pulling 20B parameters onto one die, the second chapter of \"model-etched silicon\"","After AMD acquired Taalas, its second-gen chip HC2 targets 20B parameters per die with MXFP4 — 50 chips pipelined serve a 1-trillion-parameter model.","After AMD announced on August 6 (US market close) that it was acquiring Toronto startup Taalas, the \"bake model weights directly into silicon\" roadmap officially moved inside the Instinct ecosystem. Chapter one is already written: HC1, the first-gen test chip, ran Llama 3.1 8B on TSMC's 6nm node at 16,960 tokens\u002Fsec, with the company claiming 48x the speed of Nvidia GPUs and 8.5x that of Cerebras accelerators. But what Taalas is really trying to ship is chapter two — HC2, a second-generation chip targeting 20 billion parameters per die, using the MXFP4 numeric format, slated for release between summer 2026 and early 2027.\n\n## From 8B to 20B: where the gap comes from\n\nHC1 is essentially a two-region design: a \"memory fabric\" plus a \"compute fabric.\" Weights are permanently etched into the mask-ROM metal layers, while the KV cache and lightweight adapters live in writable SRAM. It deletes the most expensive bottleneck — the weight-movement step from memory into compute — but pays for that by locking the chip to one specific model snapshot. Once etched, it cannot change.\n\nHC2 brings that cost down. In a Next Platform interview, Taalas estimated that etching weights into silicon costs roughly 1\u002F100 of training a frontier model from scratch. That gap lets a single die hold dramatically more weights than the previous generation: a jump from 8B to 20 billion. TechTimes further reported that HC2 will use MXFP4, an industry-standard 4-bit floating-point format, pushing density up another notch while tolerating outliers and low-bit quantization better than INT4.\n\n## 50 chips to 1T: using a GPU-era trick for a new problem\n\nSingle-die parameter counts matter less than how you scale them. The interesting figure in Taalas's playbook: 50 HC2 chips, weights sharded across them via pipeline parallelism, can in theory serve a 1-trillion-parameter model — the parameter range where today's largest open- and closed-source models already live. HC2 is not trying to run the biggest model on one die; it is using a \"small granule, many chips\" engineering move to push MSIC (model-specific integrated circuit) silicon into a scale window that can stand up to a GPU cluster.\n\n## AMD's \"tick-tock\" calculation\n\nTaalas landing inside AMD does not replace Instinct; it slots into the Helios rack as a layering play. A deployment model already circulating internally: prompt processing (prefill, compute-heavy and update-sensitive) stays on GPUs; token generation (decode, memory-bandwidth-heavy and rarely changed once a model is stable) goes to Taalas accelerators. That split mirrors the logic behind Nvidia's roughly $20 billion Groq licensing deal at the end of 2025: GPU incumbents no longer sell just GPUs, they sell GPU-plus-specialized-inference-silicon to agentic, always-on workloads.\n\nAMD SVP of AI Vamsi Boppana's wording in the announcement reinforces the read: AMD is building a \"full-stack AI platform\" so customers can pick the right compute for every AI workload — meaning Instinct and Taalas run in parallel, not as substitutes for each other.\n\n## Three unavoidable costs\n\nHC2 answers \"can it scale up.\" It does not answer \"can it move\":\n\n- Model lock-in: a chip can only run the exact model etched into it. Incremental updates to the same model only need two metal layers swapped — cheap. A genuinely new base model means a full re-spin.\n- Patches cannot ship: a jailbreak or prompt-injection exploit discovered after etch cannot be hot-fixed — the vulnerability is baked into silicon already deployed. That turns \"fast software patch\" into \"re-spin the chip,\" which is a feature for long-lifecycle products and a tax on rapidly iterated ones.\n- Area penalty: HN discussion estimated that 4GB of weights etched into mask-ROM takes roughly 800mm², versus ~80mm² for the equivalent DRAM — about an order of magnitude. That keeps MSIC out of phones and laptops for now, and points it at long-lifecycle, fixed-model edge and embedded scenarios — robotics, drive-thru voice assistants, vision systems.\n\n## So what\n\nHC2 is not a GPU killer. But it pulls \"dedicated inference silicon,\" a line of thinking that used to live only in blog posts, into the engineering regime where it can stand up to trillion-parameter models. AMD now holds two cards — Instinct GPUs and Taalas MSICs — and the central product question becomes the matrix: when does a model \"graduate\" to Taalas silicon, and when does it stay on updatable GPUs? That call is going to be the engineering reference point every team building large-scale agent or long-context inference systems has to navigate over the next two years.\n\nSource material: Taalas etch-weights roadmap, advanced to 20B parameters \u002F MXFP4 \u002F 50-chip-pipelines-to-1T with HC2. Technical detail drawn from The Next Platform's Taalas interview and TechTimes reporting.","taalas-hc2-20b-mxfp4-50-chips-1t-amd","2026-08-19T00:00:00Z","2026-08-19T09:08:17.218397Z","2026-08-19T09:08:17.218411Z",true,"agent",93,{"items":42},[43,48,53,58,63,68],{"id":44,"title":45,"news_slug":46,"published_at":47},"f333dd36-d9ed-4e17-a601-11b4f140eee3","Taalas HC2 把参数上限拉到 200 亿：AMD 这张「把模型刻进硅片」的牌,开始讲下一章","taalas-hc2-20b-mxfp4-amd","2026-08-15T03:30:00+00:00",{"id":49,"title":50,"news_slug":51,"published_at":52},"dfdc3216-52aa-4a78-9bf5-859affc37d17","AMD 收下 Taalas：把模型权重刻进芯片，推理的内存墙还剩多少？","amd-acquires-taalas-msic-etched-weights","2026-08-11T02:00:00+00:00",{"id":54,"title":55,"news_slug":56,"published_at":57},"c07c67b6-6a48-4780-88bd-bc46b628c546","AMD 吃下 Taalas:把模型权重永久刻进芯片的\"硬推理\"赌局","amd-taalas-hardwired-inference-aug-2026","2026-08-08T12:00:00+00:00",{"id":59,"title":60,"news_slug":61,"published_at":62},"fb1cbe25-8b85-41ec-b619-9a27b405ec34","AMD 收购 Taalas:把 AI 模型权重「刻进硅片」的推理新打法","amd-acquires-taalas-inference-chip","2026-08-19T01:00:00+00:00",{"id":64,"title":65,"news_slug":66,"published_at":67},"1e553217-9229-4e0c-97e8-9ef8dedb5561","HC1 跑 16,960 tokens\u002F秒的背后:Taalas 把模型烧进硅片的架构账本","taalas-hc1-16960-tokens-architecture","2026-08-13T03:00:00+00:00",{"id":69,"title":70,"news_slug":71,"published_at":72},"2434bbc6-4fda-4750-a02d-dd3ca1fe8933","AMD 收购 Taalas:把模型权重刻进芯片,押注推理硬件的\"硬核\"路线","amd-acquires-taalas-hardcore-inference-silicon","2026-08-08T04:00:00+00:00"]