Taalas HC2: 20B Parameters + MXFP4, the "model-baked-into-silicon" gamble enters chapter two

On August 6 at US market close, AMD announced its acquisition of Toronto-based startup Taalas, pulling a company that etches model weights directly into chip silicon into the Instinct ecosystem. Chapter one of this story has already been told: HC1, fabricated on TSMC's 6nm node, runs Llama 3.1 8B at 16,960 tokens/second — Taalas claims 48x faster than Nvidia GPUs and 8.5x faster than Cerebras accelerators. But what Taalas is really trying to ship is chapter two — the second-generation HC2 chip, targeting 20 billion parameters per die with the MXFP4 numeric format, due out summer 2026 to early 2027. The Register was the first to write this roadmap into public reporting.

From 8B to 20B: where the gap shows up

HC1's essence is a dual-region structure — mask-ROM "recall fabric" + SRAM "recall fabric": model weights are permanently etched into the metallization layers, while KV caches and lightweight adapters live in updatable SRAM. It eliminates the most expensive bottleneck — moving weights to the compute unit — but it also locks the chip to one specific model snapshot. Once etched, it can't change.

HC2 compresses the cost of that path. In an interview with The Next Platform, Taalas estimated that etching weights into silicon costs roughly 1/100 of training a frontier model from scratch. That means the weight capacity inside a single chip can scale far more aggressively than the previous generation: from 8B up to 20B. TechTimes reported HC2 will adopt MXFP4, an industry-standard 4-bit floating-point format — one more density step up, with better tolerance for outliers and low-bit quantization than INT4.

50 chips pipeline-parallel = 1T: solving a new problem with the GPU era's old technique

Single-die parameter count only tells half the story. The interesting part is Taalas's scaling ledger: 50 HC2 chips, using pipeline parallelism to split weights, could in principle serve a 1-trillion-parameter model — exactly the parameter range where today's largest open and closed models sit. In other words, HC2 doesn't aim to maximize per-chip size; it uses a "small grain, many chips" engineering approach to push the MSIC (model-specific integrated circuit) play into the scale window where it can compete head-on with GPU clusters.

AMD's "tick-tock" calculation

After Taalas joins the AMD family, the likely play isn't to replace Instinct — it's to slot into Helios racks as a layered tier. One deployment model already circulating inside: prompt processing stays on GPUs (prefill is compute-intensive and update-flexible), token generation hands off to Taalas accelerators (decode is memory-bandwidth-bound, single-shot latency-sensitive, and once a model is stable it rarely changes). This split mirrors the logic behind Nvidia's roughly $20B Groq licensing deal in late 2025: GPU vendors no longer sell just GPUs — they sell a portfolio that bundles specialized inference silicon alongside, all aimed at "agentic, always-on" workloads.

Three unavoidable costs

HC2 answers "can it scale?" — it does not answer "can it move?":

  • Model lock-in: A single chip runs only the model etched into it at fab time. Incremental updates of the same model need only two metal layers reworked — manageable cost. But a brand-new base model means a full chip re-spin.
  • No security patches: Once a jailbreak or prompt injection is discovered, the etched-in version can't be hot-patched. That turns the traditional "ship a software fix fast" into "refab the chip." For long-lifecycle products this is a feature; for products that iterate weekly, it's a tax.
  • Area penalty: An HN commenter estimated that etching 4GB of weights in mask-ROM takes roughly 800mm², versus about 80mm² for equivalent-capacity DRAM — an order of magnitude more. That rules out phones and laptops in the near term. The fit is long-lifecycle, fixed-model edge and embedded — robotics, drive-thru voice agents, vision systems.

So what

HC2 isn't a GPU killer. But it pulls "specialized inference silicon" — a topic that used to live only in blog posts — into the engineering tier where it can serve trillion-parameter models. AMD now holds Instinct GPUs + Taalas MSIC simultaneously. The real question is matrix positioning: when does a model "graduate" to Taalas silicon, and when does it stay on the updatable GPU? That judgment will become an unavoidable engineering reference point for every team building large-scale agent or long-context inference over the next two years.

Original source: AMD is using Taalas to etch model weights into silicon, and HC2 pushes the story to its next chapter — 20B parameters / MXFP4 / 50 chips for 1T. Technical breakdown at ExplainX.