[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"news-slug-taalas-hc2-20b-mxfp4-amd":3,"news-related-f333dd36-d9ed-4e17-a601-11b4f140eee3":38},{"id":4,"title":5,"summary":6,"content":7,"original_url":8,"source_id":9,"tags":10,"translations":24,"news_slug":31,"published_at":32,"created_at":33,"modified_at":34,"is_published":35,"publish_type":36,"image_url":14,"view_count":37},"f333dd36-d9ed-4e17-a601-11b4f140eee3","Taalas HC2 把参数上限拉到 200 亿：AMD 这张「把模型刻进硅片」的牌,开始讲下一章","Taalas 第二代芯片 HC2 目标每片 200 亿参数,采用 MXFP4 数值格式,2026 年夏至 2027 年初推出;50 片用 pipeline parallelism 即可拼出 1 万亿参数模型。本文拆解 HC2 的工程账本、AMD 的分层部署策略,以及「刻死在硅片上」带来的三个不能回避的代价。","# Taalas HC2:20B 参数 + MXFP4,把「模型烧进硅片」的赌局讲到第二章\n\nAMD 在 8 月 6 日收盘后宣布收购多伦多初创公司 Taalas,把一家做「把模型权重直接刻进芯片」的小公司收进了 Instinct 体系。这件事的第一章已经讲过 ——HC1 用台积电 6nm 工艺跑 Llama 3.1 8B,做到 16,960 tokens\u002F秒,Taalas 自称比英伟达 GPU 快 48 倍,比 Cerebras 加速器快 8.5 倍。但 Taalas 真正想交付的,其实是第二章:第二代芯片 HC2,目标每片 200 亿参数,采用 MXFP4 数值格式,2026 年夏至 2027 年初推出。[The Register](https:\u002F\u002Fwww.theregister.com\u002Fsystems\u002F2026\u002F08\u002F06\u002Famd-acquires-ai-chip-startup-taalas-to-boost-inference-performance-by-etching-models-into-silicon\u002F5284344) 把这条路线图第一次写进了公开报道。\n\n## 从 8B 到 200 亿,差在哪儿\n\nHC1 的本质是 mask-ROM「记忆 fabric」+ SRAM「记忆 fabric」的双区结构:模型权重永久刻在金属层,KV 缓存和轻量适配器放在可写的 SRAM 里。它把\"权重搬移到计算单元\"这一最贵的瓶颈直接消掉,但也把芯片锁死在某个具体的模型快照上 —— 一旦刻好,改不了。\n\nHC2 把这条路的代价压了下来。Taalas 在 The Next Platform 的一次访谈中估算,把权重刻进硅片的成本大约只有从头训练一个前沿模型的 1\u002F100。这意味着同一颗芯片里能容纳的权重规模,可以比上一代激进得多:从 8B 抬到 200 亿。TechTimes 报道指 HC2 将采用 MXFP4 这种行业标准的 4-bit 浮点格式,密度再上一个台阶,但对极端值和低比特量化的容忍度比 INT4 更好。\n\n## 50 片拼 1T:用 GPU 时代的老办法解决新问题\n\n只谈单片参数意义有限,真正有意思的是 Taalas 给出的扩展账本:50 片 HC2 用 pipeline parallelism 把权重切分,理论上就能跑 1 万亿参数的模型 —— 这正是今天最大规模开源和闭源模型所在的参数区间。换言之,HC2 不追求单片跑得最大,而是用「小颗粒、多芯片」的工程办法,把 MSIC(model-specific integrated circuit)这张牌推到能与 GPU 集群正面竞争的规模窗口。\n\n## AMD 的「tick-tock」算盘\n\nTaalas 进 AMD 体系后,大概率不是要取代 Instinct,而是要塞进 Helios 机柜做分层。一种已经在内部流传的部署模型是:**Prompt 处理留在 GPU** 上做(预填充是计算密集、对更新灵活度敏感),**token 生成交给 Taalas 加速器**(解码是访存密集、对单次延迟敏感,且模型一旦稳定就很少改动)。这种拆分与英伟达 2025 年底花约 200 亿美元拿下 Groq 授权许可的逻辑同源:GPU 厂商不再只卖 GPU,而是把专用推理硅挂在自己体系边上,一起卖给「agentic、always-on」的工作负载。\n\n## 三个没法回避的代价\n\nHC2 解决的是「能不能做大」,没解决的是「能不能动」:\n\n- **模型锁死**:一张芯片只能跑刻进去那一刻的模型。同一型号增量更新只需换两层金属层,成本可控;但要是换一个全新基座模型,就是完整流片。\n- **安全补丁失效**:任何 jailbreak 或 prompt injection 一旦发现,刻在硬件里的版本没法热修。这把传统的「软件快速打补丁」变成「重新流片」,对长生命周期产品反而是优点,对持续迭代的产品反而是负担。\n- **面积代价**:HN 讨论里有人估算过,4GB 权重用 mask-ROM 刻大约要 800mm²,而同样容量的 DRAM 只要 80mm² 左右,差一个数量级。这意味着短期内它进不了手机、笔记本,更适合长生命周期、固定模型的边缘 \u002F 嵌入式场景 —— 比如机器人、drive-thru 语音助手、视觉系统。\n\n## 所以呢\n\nHC2 不是 GPU killer,但它把「专用推理硅片」这条原本只在博客文章里出现的思路,拉到了可以正面承接 1 万亿参数模型的工程量级。AMD 现在手里同时有 Instinct GPU + Taalas MSIC 两张牌,关键问题是产品矩阵怎么排:什么时候让模型「毕业」到 Taalas 硅片上,什么时候继续留在可更新的 GPU 上 —— 这个判断会成为接下来两年所有想做大规模 agent \u002F 长上下文推理的团队,绕不开的工程参考点。\n\n原始出处:AMD 通过 Taalas 把模型权重刻进芯片,而 HC2 把这件事推到了 200 亿参数 \u002F MXFP4 \u002F 50 片拼 1T 的下一章。技术细节详见 [ExplainX 的拆解](https:\u002F\u002Fwww.explainx.ai\u002Fblog\u002Famd-taalas-acquisition-etched-silicon-chip-august-2026)。","https:\u002F\u002Fwww.theregister.com\u002Fsystems\u002F2026\u002F08\u002F06\u002Famd-acquires-ai-chip-startup-taalas-to-boost-inference-performance-by-etching-models-into-silicon\u002F5284344","ec2dc025-8d7e-442b-9b19-b58a5e52a59f",[11,15,18,21],{"id":12,"name":13,"slug":13,"description":14,"color":14},"40269b40-7942-4650-9672-ed2e6524d37a","ai-technology",null,{"id":16,"name":17,"slug":17,"description":14,"color":14},"e0d31e94-ce47-4c8f-831c-d3d2926d42f3","hardware",{"id":19,"name":20,"slug":20,"description":14,"color":14},"0a93ec8e-ea39-4693-81de-563ca8c173f7","inference",{"id":22,"name":23,"slug":23,"description":14,"color":14},"7e89b5cc-57db-4f37-bc6d-28919a73931c","model-release",[25],{"id":26,"lang":27,"title":28,"summary":29,"content":30},"2a7710be-17b4-4de0-a239-eee0ca003a41","en","Taalas HC2 raises the limit to 20B parameters on silicon","Taalas's second-generation chip HC2 targets 20 billion parameters per die, adopts the MXFP4 numeric format, and is due out summer 2026 to early 2027; 50 chips pipeline-parallel could serve a trillion-parameter model. This piece breaks down HC2's engineering ledger, AMD's tiered deployment strategy, and the three unavoidable costs of \"baking into silicon.\"","# Taalas HC2: 20B Parameters + MXFP4, the \"model-baked-into-silicon\" gamble enters chapter two\n\nOn August 6 at US market close, AMD announced its acquisition of Toronto-based startup Taalas, pulling a company that etches model weights directly into chip silicon into the Instinct ecosystem. Chapter one of this story has already been told: HC1, fabricated on TSMC's 6nm node, runs Llama 3.1 8B at 16,960 tokens\u002Fsecond — Taalas claims 48x faster than Nvidia GPUs and 8.5x faster than Cerebras accelerators. But what Taalas is really trying to ship is chapter two — the second-generation HC2 chip, targeting 20 billion parameters per die with the MXFP4 numeric format, due out summer 2026 to early 2027. [The Register](https:\u002F\u002Fwww.theregister.com\u002Fsystems\u002F2026\u002F08\u002F06\u002Famd-acquires-ai-chip-startup-taalas-to-boost-inference-performance-by-etching-models-into-silicon\u002F5284344) was the first to write this roadmap into public reporting.\n\n## From 8B to 20B: where the gap shows up\n\nHC1's essence is a dual-region structure — mask-ROM \"recall fabric\" + SRAM \"recall fabric\": model weights are permanently etched into the metallization layers, while KV caches and lightweight adapters live in updatable SRAM. It eliminates the most expensive bottleneck — moving weights to the compute unit — but it also locks the chip to one specific model snapshot. Once etched, it can't change.\n\nHC2 compresses the cost of that path. In an interview with The Next Platform, Taalas estimated that etching weights into silicon costs roughly 1\u002F100 of training a frontier model from scratch. That means the weight capacity inside a single chip can scale far more aggressively than the previous generation: from 8B up to 20B. TechTimes reported HC2 will adopt MXFP4, an industry-standard 4-bit floating-point format — one more density step up, with better tolerance for outliers and low-bit quantization than INT4.\n\n## 50 chips pipeline-parallel = 1T: solving a new problem with the GPU era's old technique\n\nSingle-die parameter count only tells half the story. The interesting part is Taalas's scaling ledger: 50 HC2 chips, using pipeline parallelism to split weights, could in principle serve a 1-trillion-parameter model — exactly the parameter range where today's largest open and closed models sit. In other words, HC2 doesn't aim to maximize per-chip size; it uses a \"small grain, many chips\" engineering approach to push the MSIC (model-specific integrated circuit) play into the scale window where it can compete head-on with GPU clusters.\n\n## AMD's \"tick-tock\" calculation\n\nAfter Taalas joins the AMD family, the likely play isn't to replace Instinct — it's to slot into Helios racks as a layered tier. One deployment model already circulating inside: **prompt processing stays on GPUs** (prefill is compute-intensive and update-flexible), **token generation hands off to Taalas accelerators** (decode is memory-bandwidth-bound, single-shot latency-sensitive, and once a model is stable it rarely changes). This split mirrors the logic behind Nvidia's roughly $20B Groq licensing deal in late 2025: GPU vendors no longer sell just GPUs — they sell a portfolio that bundles specialized inference silicon alongside, all aimed at \"agentic, always-on\" workloads.\n\n## Three unavoidable costs\n\nHC2 answers \"can it scale?\" — it does not answer \"can it move?\":\n\n- **Model lock-in**: A single chip runs only the model etched into it at fab time. Incremental updates of the same model need only two metal layers reworked — manageable cost. But a brand-new base model means a full chip re-spin.\n- **No security patches**: Once a jailbreak or prompt injection is discovered, the etched-in version can't be hot-patched. That turns the traditional \"ship a software fix fast\" into \"refab the chip.\" For long-lifecycle products this is a feature; for products that iterate weekly, it's a tax.\n- **Area penalty**: An HN commenter estimated that etching 4GB of weights in mask-ROM takes roughly 800mm², versus about 80mm² for equivalent-capacity DRAM — an order of magnitude more. That rules out phones and laptops in the near term. The fit is long-lifecycle, fixed-model edge and embedded — robotics, drive-thru voice agents, vision systems.\n\n## So what\n\nHC2 isn't a GPU killer. But it pulls \"specialized inference silicon\" — a topic that used to live only in blog posts — into the engineering tier where it can serve trillion-parameter models. AMD now holds Instinct GPUs + Taalas MSIC simultaneously. The real question is matrix positioning: when does a model \"graduate\" to Taalas silicon, and when does it stay on the updatable GPU? That judgment will become an unavoidable engineering reference point for every team building large-scale agent or long-context inference over the next two years.\n\nOriginal source: AMD is using Taalas to etch model weights into silicon, and HC2 pushes the story to its next chapter — 20B parameters \u002F MXFP4 \u002F 50 chips for 1T. Technical breakdown at [ExplainX](https:\u002F\u002Fwww.explainx.ai\u002Fblog\u002Famd-taalas-acquisition-etched-silicon-chip-august-2026).","taalas-hc2-20b-mxfp4-amd","2026-08-15T03:30:00Z","2026-08-15T09:03:58.488497Z","2026-08-15T09:03:58.488505Z",true,"agent",143,{"items":39},[40,45,50,55,60,65],{"id":41,"title":42,"news_slug":43,"published_at":44},"45375854-7739-4dd1-bc6a-30db4474652a","Taalas HC2:把单片参数拉到 200 亿,「模型刻进硅片」的第二章","taalas-hc2-20b-mxfp4-50-chips-1t-amd","2026-08-19T00:00:00+00:00",{"id":46,"title":47,"news_slug":48,"published_at":49},"dfdc3216-52aa-4a78-9bf5-859affc37d17","AMD 收下 Taalas：把模型权重刻进芯片，推理的内存墙还剩多少？","amd-acquires-taalas-msic-etched-weights","2026-08-11T02:00:00+00:00",{"id":51,"title":52,"news_slug":53,"published_at":54},"c07c67b6-6a48-4780-88bd-bc46b628c546","AMD 吃下 Taalas:把模型权重永久刻进芯片的\"硬推理\"赌局","amd-taalas-hardwired-inference-aug-2026","2026-08-08T12:00:00+00:00",{"id":56,"title":57,"news_slug":58,"published_at":59},"cdc8e3ce-b1aa-4348-9436-04763179af9c","AMD MI455X：Transformers 99.5% 通过率，432GB HBM4","amd-mi455x-huggingface-99-5","2026-07-27T10:30:00+00:00",{"id":61,"title":62,"news_slug":63,"published_at":64},"bac63469-b19c-4619-8709-73656ad0cd9f","Intel × HF 上线 xpu-kernels Skill：LLM Agent 把 vLLM 调过的 Triton 内核再提 2.8×","intel-hf-xpu-kernels-skill-triton-2-8x","2026-06-20T00:16:00+00:00",{"id":66,"title":67,"news_slug":68,"published_at":69},"ffb44de4-c5e2-4e4c-8828-492716fc5c18","Grok 4.3 入驻 Amazon Bedrock：xAI 的多云矩阵拼上 AWS 那一块，Mantle 才是真正主角","grok-4-3-bedrock-mantle-openai-compatible","2026-06-17T08:05:00+00:00"]