[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"news-slug-taalas-hc1-16960-tokens-architecture":3,"news-related-1e553217-9229-4e0c-97e8-9ef8dedb5561":38},{"id":4,"title":5,"summary":6,"content":7,"original_url":8,"source_id":9,"tags":10,"translations":24,"news_slug":31,"published_at":32,"created_at":33,"modified_at":34,"is_published":35,"publish_type":36,"image_url":14,"view_count":37},"1e553217-9229-4e0c-97e8-9ef8dedb5561","HC1 跑 16,960 tokens\u002F秒的背后:Taalas 把模型烧进硅片的架构账本","AMD 8 月 6 日完成对 Taalas 的收购。HC1 用台积电 6nm 工艺跑 Llama 3.1 8B 达到 16,960 tokens\u002F秒,比 NVIDIA GPU 快 48 倍、比 Cerebras 快 8.5 倍。HC2 单芯片目标 200 亿参数,50 片级联可支持万亿参数模型,但模型被流片后就锁死,只有换两层 metal mask 就能升级、换基模则要重做整片芯片。","# AMD 收下 Taalas 之后：把模型权重刻进芯片，推理的下一站在哪？\n\n8 月 6 日美股收盘后，AMD 官宣收购多伦多初创 Taalas。这家 2023 年才成立的小公司不卖通用加速器，它做的事很简单也很激进——**把模型权重直接蚀刻进芯片本身**。配合这个时间节点看，NVIDIA 早在 2025 年 12 月就和 Groq 谈下了约 200 亿美元的推理 IP 授权；AMD 这次是把\"为单一模型造芯\"的路子整个收进自己的 Instinct 体系里。\n\n## 数字先摆出来\n\nTaalas 在 2026 年 2 月公开的测试芯片 HC1，用台积电 6nm 工艺制造，单卡跑 Meta 的 **Llama 3.1 8B 跑到 16,960 tokens\u002F秒**。官方口径里这个速度比 NVIDIA GPU 快 48 倍，比 Cerebras 加速器快 8.5 倍。芯片面积 815mm²，53B 晶体管，2.5kW 单卡功耗。值得提醒一句：这是 Taalas 自家披露的 vendor claim，并不是第三方独立跑分；目前能在 chatjimmy.ai 上挂到真硬件做公开 demo，Hacker News 上实测到的速度区间在 14,000–17,000 tokens\u002F秒之间。\n\n数字之外更有意思的是架构。HC1 把芯片划成两块：\n- **Mask-ROM \"recall fabric\"**：模型的权重在流片时永久烧进晶体管之间的连线里\n- **SRAM \"recall fabric\"**：一小块可改写的区域，放 KV cache 和 LoRA 适配器\n\n这意味着推理时**不再需要从 HBM\u002FDRAM 反复把权重搬运到计算单元**。访存墙——也就是当下所有 LLM 推理最贵的成本——被直接干掉了。\n\n## HC2 把天花板推到 200 亿参数\n\n按 Taalas 的计划，HC2 会在 2026 年夏天推出，单芯片目标 200 亿参数。从数学上推：50 片 HC2 通过 pipeline parallelism 级联，理论上就能跑通 1 万亿参数的模型。这和今天大模型推理的多卡部署走的是同一条路，只是换成了\"硬编码权重\"。\n\n但这就是关键代价——**模型一旦被蚀刻进硅，就和那一片芯片永久绑死**。想要更新到 Llama 3.2 怎么办？Taalas 的方案是只换两层 metal mask，不用从零重做整片芯片；想要换整个新基模？对不起，**从零重新流片**。\n\n## 灵活性 vs 速度：三条硬约束\n\n把这件事放到 AI 基础设施的版图上看，有三条线卡死了 MSIC 不会一夜替代 GPU：\n\n1. **更新周期对不上**。前沿实验室现在基本是按月发版，一个模型被刻进芯片 6 个月后，新版已经在端上了——硬件\"过期\"的速度会快过消费电子。\n2. **冻结的模型没法打补丁**。一旦发现 jailbreak 或 prompt injection，硅片里的漏洞没法靠软件热修，所有部署出去的设备都带病。\n3. **面积换算术不划算**。HN 社区估算，HC1 这种密度下存 4GB 权重需要约 800mm² 硅片，等价 DRAM 只需要约 80mm²——10 倍面积惩罚。手机这种对功耗和面积都极敏感的设备短期装不进去。\n\n## 真正的用武之地：长生命周期的\"窄\"产品\n\n把上面的限制反过来读，MSIC 的甜点场景反而清晰了：长寿周期 + 模型固定 + 低延迟 + 低功耗的窄产品。Robotics、Drive-thru 点单、车载视觉系统——这些场景的共同点是**模型上线后基本不需要换**，把模型权重刻死反而是 feature，不是 bug。\n\nAMD 的 SVP of AI Vamsi Boppana 把这次收购的定位讲得很克制：\"AMD 正在打造全栈 AI 平台，让客户能为每一类 AI 工作负载选到合适的算力。\"言下之意：HC1\u002FHC2 不是用来替代 MI355X 的，是拿来**和 Instinct GPU 配对**的——prompt 处理这种重计算留在 GPU 上，token 生成这种访存密集的活交给 Taalas 加速器。\n\n## 推理成本曲线会怎么走\n\n如果 Taalas 的 10–50x speedup 和每 token 成本在量产后真的能兑现，**最直接的二阶影响是 test-time scaling**。现在让模型\"多想一会儿\"再去回答是减幻觉最稳的方法之一，但代价是 token 暴增、延迟翻倍。推理芯片把每 token 成本砍一个数量级，模型就有空间把思考预算拉得更长，幻觉控制这件事的天花板会被悄悄推高。\n\n另一条不能忽视的线是 NVIDIA 的反应。Groq 的 IP 已经在 2025 年 12 月装进了 NVIDIA 的产品线，Cerebras 在 wafer-scale 这条路上一路狂奔（今年 GTC 上用 Gemma 4 31B 跑到 1,851 tokens\u002F秒）。AMD 这次收 Taalas 把\"专用推理硅\"这张桌子掀到了第 N 层——**通用 GPU + 专用推理加速器**的混合架构，从单家实验变成了行业共识。\n\n## 所以呢\n\n对关注 AI 基础设施的人来说，AMD-Taalas 不是\"GPU 杀手\"新闻，而是一个明确信号：**推理市场的分层已经开始**。训练还要靠 NVIDIA H100\u002FB100\u002FGB200 这类大算力 GPU；推理则会被拆成 prefill 用 GPU、decode 用专用芯片、再加上边缘用 MSIC 这种更激进的方案。闭源大模型按月发版的节奏，会把\"灵活性\"持续抬到比\"极致性能\"更高的优先级；反过来，那些模型固定、产品长寿的边缘\u002F机器人\u002F车载场景，会是 MSIC 真正落地的地方。\n\n8 月 6 日是一个时间节点，但 Taalas 收购真正的余震，要等到 HC2 出片、跑通 200 亿参数那一天才会完全释放。","https:\u002F\u002Fwww.explainx.ai\u002Fblog\u002Famd-taalas-acquisition-etched-silicon-chip-august-2026","ec2dc025-8d7e-442b-9b19-b58a5e52a59f",[11,15,18,21],{"id":12,"name":13,"slug":13,"description":14,"color":14},"fca9258a-9430-455a-b95d-b9fae5e373a8","ai-inference",null,{"id":16,"name":17,"slug":17,"description":14,"color":14},"0ef8513a-0a26-42f0-b6f9-5b6dadded45c","efficiency",{"id":19,"name":20,"slug":20,"description":14,"color":14},"e0d31e94-ce47-4c8f-831c-d3d2926d42f3","hardware",{"id":22,"name":23,"slug":23,"description":14,"color":14},"0a93ec8e-ea39-4693-81de-563ca8c173f7","inference",[25],{"id":26,"lang":27,"title":28,"summary":29,"content":30},"7ff8cd30-f14e-4da1-b6ca-9112128fe067","en","HC1 hits 16,960 tokens\u002Fs with models burned into silicon","AMD closed the Taalas acquisition on August 6. HC1, on TSMC 6nm, served Llama 3.1 8B at 16,960 tokens\u002Fsec — 48x faster than NVIDIA GPUs, 8.5x faster than Cerebras. HC2 targets 20B parameters per chip; 50 chips pipelined could serve a trillion-parameter model. The trade-off: once etched, the model is locked to that chip — only two metal masks need to change for a minor version, but a new base model requires a full re-spin.","# AMD Buys Taalas: Etching Model Weights Into Silicon and What Comes Next for Inference\n\nAfter the US market close on August 6, AMD officially closed its acquisition of Toronto-based startup Taalas. Founded in 2023, this small company does not sell general-purpose accelerators — what it does is simple and radical: **etch model weights directly into the chip itself**. In context, NVIDIA had already signed a roughly $20 billion inference IP licensing deal with Groq back in December 2025; AMD's move pulls the entire \"build a chip for one model\" approach into its Instinct ecosystem.\n\n## The numbers, up front\n\nTaalas's test chip HC1, publicly disclosed in February 2026, was fabricated on TSMC's 6nm process and ran Meta's **Llama 3.1 8B at 16,960 tokens\u002Fsecond** per chip. By the company's own claim, that's 48x faster than NVIDIA GPUs and 8.5x faster than Cerebras accelerators. The chip occupies 815mm², packs 53B transistors, and draws 2.5kW per board. Caveat: these are vendor figures, not independent third-party benchmarks; a public live demo running on real Taalas silicon is available at chatjimmy.ai, and Hacker News testers have measured 14,000–17,000 tokens\u002Fsecond in practice.\n\nThe more interesting story is the architecture. HC1 splits the die into two regions:\n- **Mask-ROM \"recall fabric\"**: model weights permanently burned into the wiring between transistors during fabrication\n- **SRAM \"recall fabric\"**: a small, rewritable region that holds the KV cache and LoRA adapters\n\nThe implication: at inference time, **the weights no longer need to be streamed from HBM\u002FDRAM to the compute units**. The memory wall — the single most expensive cost in today's LLM inference — is removed at the hardware level.\n\n## HC2 pushes the ceiling to 20 billion parameters\n\nPer Taalas's roadmap, HC2 will ship in summer 2026 with a target of 20 billion parameters per chip. Mathematically, roughly 50 HC2 chips pipelined together could, in principle, serve a 1-trillion-parameter model. That is the same multi-GPU serving topology used today, just transposed onto a \"hardcoded weights\" substrate.\n\nBut here is the key cost: **once a model is etched into silicon, that chip is permanently bound to it**. Want to update to Llama 3.2? Taalas's workaround is to swap just two metal masks, not re-fabricate the full chip. Want to switch to a different base model entirely? Sorry — **full re-spin from scratch**.\n\n## Three hard constraints that keep MSIC from replacing GPUs overnight\n\nStepping back to the broader AI infrastructure picture, three lines of friction prevent MSIC from unseating general-purpose GPUs:\n\n1. **Update cadence mismatch**. Frontier labs now ship on a near-monthly cadence. A model etched into silicon in month zero is already stale by month six — hardware \"ages\" faster than consumer electronics.\n2. **Frozen models cannot be patched**. If a jailbreak or prompt-injection exploit is discovered after deployment, there is no software patch path; every device in the field carries the baked-in vulnerability.\n3. **Area economics are not in MSIC's favor**. HN estimates put HC1-class density at roughly 800mm² of mask-ROM to hold 4GB of weights, versus about 80mm² for equivalent capacity in conventional DRAM — a 10x area penalty. Power- and area-constrained form factors like phones are out of reach for the foreseeable future.\n\n## The real use case: \"narrow\" products with long lifecycles\n\nRead the constraints the other way, and the sweet spot for MSIC sharpens: long lifecycle + fixed model + low latency + low power, in narrow products. Robotics, drive-thru order-taking, automotive vision systems — what these have in common is that **the model rarely needs to change after launch**. Freezing the weights into silicon becomes a feature, not a limitation.\n\nAMD's SVP of AI, Vamsi Boppana, framed the deal conservatively: \"AMD is building a full-stack AI platform that gives customers the flexibility to deploy the right compute solutions for every AI workload.\" The subtext: HC1\u002FHC2 is not here to replace MI355X, but to **pair with Instinct GPUs** — prompt processing (prefill), which is compute-bound, stays on GPUs; token generation (decode), which is memory-bound, gets offloaded to Taalas accelerators.\n\n## How the inference cost curve bends\n\nIf Taalas's 10–50x speedup and per-token cost claims hold at production scale, the most direct second-order effect lands on **test-time scaling**. Letting a model \"think longer\" before answering is one of the more reliable ways to reduce hallucinations today, but it is slow and token-expensive. Cut the per-token cost by an order of magnitude and the model gains headroom to spend more reasoning budget per query without breaking latency or cost — quietly pushing the ceiling on hallucination control.\n\nThe other thread is NVIDIA's response. Groq IP has been in NVIDIA's product line since December 2025; Cerebras continues to push hard on the wafer-scale axis (Gemma 4 31B at 1,851 tokens\u002Fsec on Cerebras hardware, as shown at this year's GTC). With AMD pulling Taalas into the fold, the \"dedicated inference silicon\" table has now been flipped to layer N — **the hybrid architecture of general-purpose GPU plus specialized inference accelerator has moved from one-off experiment to industry consensus**.\n\n## So what\n\nFor anyone watching AI infrastructure, AMD-Taalas is not a \"GPU killer\" headline. It is a clear signal that **stratification of the inference market has already begun**. Training will still sit on high-FLOP GPUs like NVIDIA H100\u002FB100\u002FGB200; inference will be split — prefill on GPUs, decode on dedicated accelerators, and the long tail on MSIC at the edge. The frontier closed-model labs' monthly release cadence will keep \"flexibility\" permanently priced above \"peak performance\" at the top of the stack; conversely, the fixed-model, long-lifecycle edge\u002Frobotics\u002Fautomotive tier is where MSIC will actually land.\n\nAugust 6 is a marker. The real aftershock of the Taalas acquisition won't fully arrive until HC2 ships and proves out 20-billion-parameter operation.","taalas-hc1-16960-tokens-architecture","2026-08-13T03:00:00Z","2026-08-13T12:04:03.895477Z","2026-08-13T12:04:03.895486Z",true,"agent",123,{"items":39},[40,45,50,55,60,65],{"id":41,"title":42,"news_slug":43,"published_at":44},"c07c67b6-6a48-4780-88bd-bc46b628c546","AMD 吃下 Taalas:把模型权重永久刻进芯片的\"硬推理\"赌局","amd-taalas-hardwired-inference-aug-2026","2026-08-08T12:00:00+00:00",{"id":46,"title":47,"news_slug":48,"published_at":49},"9dffd6b9-99bc-448c-90d8-f706b74edcba","Intel Xeon 6+ 登场：288核 E-core 架构能否重塑数据中心推理？","intel-xeon-6-plus-288-e-core-clearwater","2026-06-03T01:00:00+00:00",{"id":51,"title":52,"news_slug":53,"published_at":54},"bfd2a2e5-7c5c-4b92-a48b-d2aca19b11fe","英特尔SuperClaw：混合AI架构如何让边缘设备更聪明","intel-superclaw-hybrid-edge-70pct","2026-05-23T07:00:00+00:00",{"id":56,"title":57,"news_slug":58,"published_at":59},"45375854-7739-4dd1-bc6a-30db4474652a","Taalas HC2:把单片参数拉到 200 亿,「模型刻进硅片」的第二章","taalas-hc2-20b-mxfp4-50-chips-1t-amd","2026-08-19T00:00:00+00:00",{"id":61,"title":62,"news_slug":63,"published_at":64},"c26cb1e1-d0c0-471d-81a1-79536834a617","AMD 收下 Taalas：把 Llama 权重烧进 ASIC，推理速度把 GPU 甩在身后","amd-acquires-taalas-hardcore-asic-inference","2026-08-17T00:00:00+00:00",{"id":66,"title":67,"news_slug":68,"published_at":69},"dfdc3216-52aa-4a78-9bf5-859affc37d17","AMD 收下 Taalas：把模型权重刻进芯片，推理的内存墙还剩多少？","amd-acquires-taalas-msic-etched-weights","2026-08-11T02:00:00+00:00"]