On July 3, 2026, the ChinaXiv preprint platform of the Chinese Academy of Sciences published a paper by He Tingbo: "Time-Scaling Theory for Multi-Level Electronic Systems" V2 — this is exactly the engineering implementation version (the paper is "Teresa's Law") of the "Tau (τ) Law" that was high-profile released at ICAS (Shanghai) on May 25. V1 was a keynote, with only theoretical principles and a product roadmap; V2 is the full paper, for the first time swapping "make it" for "run it" — supplementing extensive engineering details, real measurement data, and Kirin 2026 mass-production measurement parameters. This 5/25 → 7/3 six-week timeline is exactly Huawei's key step in pushing the "Tau Law" from PR narrative to a peer-reviewable state. Tau (τ) Law in one sentence: use the "shrinking of signal propagation time constant τ" to replace "shrinking of transistor geometry" as the new principle for continued semiconductor performance improvement. Traditional Moore's Law relies on EUV to shrink transistors, but this path is blocked (for Huawei, no lithography machine); τ-scaling relies on architectural innovation to make signals travel faster, rather than on process to make transistors smaller. The practical path is LogicFolding — folding 2D planar circuits into 3D vertical stacks, shortening the physical length of the critical path. V1 gives the proposition, V2 fills in three things: first, an in-depth explanation of the physical implementation of LogicFolding; second, mass-production measurement parameters of Kirin 2026 (determining whether V1's "equivalent 1.4nm" is PR rhetoric); third, an explicit product evolution roadmap. The paper also discloses for the first time that between 2020-2026, 381 chips have been mass-produced based on the τ principle. At the commercial credibility level, the same news quotes HiSilicon's annual τ-route R&D investment of about ¥10 billion / $1.377 billion — the order of magnitude already exceeds most international top chip labs. Market reaction remains cool. From May 25 to now, related concept stocks have not shown a sustained unilateral trend, Wall Street has not yet priced the Tau Law into valuation premium; at the same time, Samsung and TSMC are also doing 3D stacking but the goal isn't to replace EUV; Counterpoint Research maintains reservations on "cost, power, thermal management, system integration" four engineering challenges. In other words: peers are walking a similar path, but Huawei is betting on a more aggressive version of "no EUV still reaches 1.4nm equivalent density". Today's significance: After V2, what the semiconductor community needs to do in the next few months is very specific — verify that the measured PPA (performance/power/area) and yield of the 2026 Fall Kirin chip can match the numbers in the V2 paper. If they match, the Tau Law upgrades from "theoretical ambition" to "engineering fact", and Huawei's squeeze on Nvidia in the Chinese AI chip market will sink from the brand level to the price-performance level; if they don't match, Tau Law V3 will inevitably need to supplement a lot of phenomenal engineering data, otherwise the industry discourse power in 2027-2028 will remain with the traditional "geometric scaling" camp.